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The logarithmic transition functions log[Pr(ri |si )] are also known as branch metrics; in the case that the decoder puts out only hard decision (estimates which coded bits were sent), ri = 1, the branch metric is the Hamming distance between ri and si The MLSE now determines the total metrics i dH (ri , si ) for all possible paths through the trellis ie, for all possible input sequences In the end, the path with the smallest metric is selected Such an optimum procedure requires large computational effort: the number of possible paths increases exponentially with the number of input bits The key idea of the Viterbi algorithm is the following: instead of computing metrics for all possible paths (working from top to bottom ) in the trellis, we work our way from the left to the right through the trellis.



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More precisely, we start with a set of possible states of the shift register (Ai , Bi , Ci , Di , where i denotes the time instant, or considered input bit) Let us now consider all paths that (from the left) lead into state A We discard any possible path s(1) if it merges at state Ai with a path s(2) that has a smaller metric As the paths run through the same state of the trellis, there is nothing that would distinguish the paths from the point of view of later states We thus choose the one with the better properties Similarly, we choose the best paths that run through the states Bi , Ci , and Di .

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After having determined the survivors for state i, we next proceed to state i + 1 (or rather, to the tuple of states Ai+1 , Bi+1 , Ci+1 , Di+1 ), and repeat the process All paths in a trellis ultimately merge in a single, well-de ned point, the all-zero state9 At this point, there is only a single survivor the sequence that was transmitted with the highest probability Example 145 Example for Viterbi decoding Figure 145 shows an example of the algorithm The basic structure of the trellis is depicted in Figure 145a; the bit sequence to be transmitted is shown in Figure 145b The metrics shown are the Hamming distances of the received sequence, ie, after the hard decision compared with the theoretically possible bit sequences in the trellis.

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We assume that at the outset the shift register is in the all-zero state Figure 145c shows the trellis for the rst 3 bits There are two possibilities for getting from state A0 to state A4 : by transmission of the source data sequence 0, 0, 0 (which corresponds to the coded bit sequence 000, 000, 000, and thus via states A2 , A3 ) or by transmission of the source data sequence 100 (coded bit sequence 111, 011, 001 ie, via states B2 , C3 ) In the former case, the branch metric is 2; in the latter, it is 6 This allows us to immediately discard the second possibility Similarly, we nd that the transition from state A0 to state B4 could be created (with greatest likelihood) by the source data sequence 0, 0, 1, and not by 1, 1, 0.

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